Doeper/ Serge VCS Expander Schematic

A description of the method I used to add Hold, Burst and EOR functions to the Doepfer A-171-2. An update to this post. The module is a licenced version of the Serge/ CGS DUSG/ VCS, so these mods will work on them too, although the pins may be different.

You can download the schematics and Fritzing file here. I wish I had done this at the time in spring as I've had to retrace my thoughts from incomplete notes. It's been fun but I might have some things wrong and I’m sure some aspects could be done better. So, please continue the discussion and post corrections and improvements to this circuit in this forum thread. I will update this post accordingly.

HOLD



The idea behind the Hold circuit is simple: interrupt the integrator. If you wanted to go no further and keep this mod passive, all you would need to do is cut one trace and hook up a switch. On the A-171-2, I found a convenient place between pin 7 of the TL084 quad opamp and the 8k2 resistor (R39).

If we want to automate this, we need an analogue switch. Transistors can be fiddly and the common CD4066 won’t process all signals, so I used a DG201. This switch is ‘normally closed’, so with no gate on the command input, drain and source are connected and the integrator’s loop is closed. Pulsing it breaks the connection.

EOR

Referring to Tim Stinchcombe’s VCS analysis and comparing with the Doepfer layout, pin 4 of the LM3900 is high during the attack phase. The ‘not attack’ gate, which will become part of our EOR gate, can be found on pin 5 of the LM3900. If you observe this output with an oscilloscope you’ll notice we need to process it as the ‘not attack’ gate remains high until the next attack phase is initiated. This can have its uses, but it’s not what we’re after if we want an EOR/ variable length gate that can be used to ping filters etc.



This is where we have to get creative and ‘patch with ICs’: we use another switch on the DG201 to operate a logical AND function. The signal which chops our ‘not attack’ gate down to the right length is the EOC gate. We can tap this signal from the End Out jack on the A-171-2. As the EOC gate is ‘high’ at the wrong time, we want to flip its activity.

The need for a logic inverter conveniently also answers the question of how to buffer the inputs for this mod. I used an HCF4049UBC Hex Inverter. As the supply voltage also determines the logic threshold for this chip (lower voltage = lower threshold/ faster response), I chose to run it off 5V, supplied by a 78L05A regulator. I sent the new EOR signal from pin 15 of the switch to a jack and an LED.

BURST

Now that we have the means to process logic, the burst function is relatively simple. It’s a circuit adaptation of the classic Maths Trills patch where we used a logic gate to interrupt the loopback of the EOC signal to the trigger input. As with the EOR gate, we use a switch to function as a logical AND gate. The DG201 is ’normally closed’, so we need to keep the switch open when there is no burst command present. To do this, we use a spare inverter to flip the activity of the burst input. Looking at the schematic on Ken Stone’s site, the trigger and cycle inputs are OR-combined by diodes, so the VCS can be triggered and burst/ cycled at the same time.



The DG201 is powered from +/- 12V. Filter the supply as usual and add 0.1uF bypass caps for the ICs. The burst and hold inputs were conditioned by cutting negative voltages. The schematic says 4001, but I used 4148 diodes.  I added a manual gate by tapping 5V and sending it via an ON-ON switch to either the burst or hold jack’s switching contact.

It sounds more complicated than it is. Once I’d thought it through, I built it on stripboard on the fly, without the need for a detailed schematic. Lesson learned on that score! I hope these notes help and look forward to your comments and improvements.

Thanks to Dieter Doepfer and Chrisi & Erik at Koma Elektronik for their help on the subject of switches.

The usual DIY disclaimer: do this at your own risk, take care and have fun.