Using a gate delay and comparator to trigger 'full length' ADSR runs, achieve looping ADSRs and delayed looping of AD envelopes. As suggested in this thread.
Unlike AD envelopes, ADSRs generally need a gate signal to fully complete their cycle. The gate determines the duration of the sustain phase of the envelope's run. So, what to do if your sequencer only generates triggers?
With a gate delay like the A-162, set the delay to zero and the length to taste. If using Maths' channel 1, the rise sets the delay time and the fall the length of the gate, available at the EOR. This provides the gate that the sustain requires. This mimics the response of AD envelopes like the VCS, which complete regardless of gate duration.
If you then mult that gate to a comparator with a suitable threshold, you'll get a second gate when the first expires. I used the Sport Modulator with the multed gate fed to the bottom input and 5V as a threshold reference sent to the top input. The middle output provides the comparator function. Mix the two gates and feed them to the input of the gate delay and you've got a looping ADSR.
The A-162 is great for these sorts of tricks and can also be used with AD envelopes which have an End Out (VCS, Maths, A-143-1) to achieve the Envelator's delayed looping.